1. Field of the Invention
The present invention relates to testing semiconductor devices including integrated circuits and, more particularly, to a compliant contact structure for connecting electrical signals to integrated circuits during testing of the integrated circuits.
2. State of the Art
Semiconductor devices, from microprocessors to memory chips, are fabricated by performing a long series of processes including depositing various materials, selectively masking, and etching on a semiconductor wafer or other bulk semiconductor substrate. Many identical integrated circuits may be fabricated on a single semiconductor wafer by forming the integrated circuits in arrays of semiconductor die locations across the wafer. Ultimately, semiconductor dice bearing the individual integrated circuits are singulated from the wafer and are either further processed, including packaging and additional testing, or discarded when they are determined to be defective in one or more aspects and the defect or defects cannot be remediated.
Due to inadequacies in processing or other defects in the semiconductor wafer, certain ones of the integrated circuits will not function as designed. Such defects may be detected initially or may not become apparent until an integrated circuit has been in operation for a period of time. Therefore, it is desirable to test and electrically stress the integrated circuits to determine which circuits are operational and which ones are defective or likely to become defective.
Semiconductor integrated circuits are typically subjected to a series of test procedures during the manufacturing process in order to verify functionality and reliability. Typical test approaches include wafer probe testing in which integrated circuits are individually tested to determine the operational characteristic of each before singulation from the semiconductor wafer.
Conventionally following initial testing, semiconductor dice bearing the integrated circuits are singulated into individual integrated circuit dice or “chips” with the operational chips usually being further assembled or otherwise processed into semiconductor die packages suitable for installation on higher-level packaging. The semiconductor die packages are then burned in by loading them into sockets on burn-in boards and electrically operating the semiconductor die packages through programmed test sequences at cyclically varied and elevated temperatures for an extended testing period. Burn-in induces premature failure in marginally operative semiconductor devices which may have passed probe testing, allowing such devices to be screened out before they are installed on higher-level packaging or sold to a third party. Burning-in and testing of packaged devices are typically accomplished through the use of sockets particularly suited for the burn-in conditions and high speed testing. Accordingly, conventional manufacturing and testing processes are expensive and time consuming because of the repeated handling and testing of individual semiconductor devices and because individually tested and handled semiconductor devices that ultimately fail have wasted costly resources and time.
A considerable advantage in cost and process time could be attained by burning-in and testing a semiconductor wafer before it is singulated into discrete devices. Additional savings may be recognized by forgoing packaging of devices that ultimately fail-once subjected to burn-in conditions. A considerable effort has been expended to develop effective methods for wafer level testing. One such approach utilizes cantilevered or spring-wire probes which are placed on a contactor or probe card for simultaneous contact to all of the devices on the semiconductor wafer. Such contactor cards are expensive to manufacture and result in undesirable electrical characteristics such as increased inductance along parallel wires. Furthermore, conventional contactor cards are generally fabricated from materials having dissimilar expansion coefficients than the semiconductor substrate, for example, a semiconductor wafer (hereinafter “wafer-under-test”) undergoing testing. Therefore, conventional contactor cards exhibit a markedly dissimilar expansion to the wafer-under-test over temperature extremes characteristic of burn-in testing and may result in misalignment of the contactor card contact pins with the corresponding integrated circuit contact pads (bond pads) on the semiconductor wafer-under-test.
Therefore, there is a need for providing a contact fabrication methodology which results in a highly economical and manufacturable, high precision apparatus for contacting bond pads of individual semiconductor devices in a wafer-level testing environment.